1. Part a)
2. Part b)
   1. Explanation
3. Part c)
4. Part d) i)
   1. Explanation/Working:
5. Part d) ii)
6. Part d) iii)
7. Part d) iv)
8. Links to Notes
   1. Attributions to media used in this post
9. Footnotes

Part a)

AND Gate:

  A | B | A AND B
  ---------------
  0 | 0 |    0
  0 | 1 |    0
  1 | 0 |    0
  1 | 1 |    1

Or Gate:

  A | B | A OR B
  ---------------
  0 | 0 |    0
  0 | 1 |    1
  1 | 0 |    1
  1 | 1 |    1

Not Gate:

  A | NOT A
  ---------
  0 |   1
  1 |   0

See this note¹

Part b)

Suggested response:

XOR truth table:

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

Output is 1 in XOR for (NOT A AND B) OR (A AND NOT B)

Circuit:

Explanation

Assume we want to use an AND gate as a building block for our resulting circuit. Wherever we have an output of 1  it means that the inputs to that and gate should also be 1 .

If we imagine an AND gate being the last gate before the output, wherever there is a 1 we need to understand that the inputs to that gate would have to be 1.

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

-For each output that produces a 1, we modify the variable input to match  the modded input listed in the specific row of the table:

Row number	A	B	A XOR B	Desired output using AND Gate
i	0	0	0
ii	0	1	1	NOT A AND B
iii	1	0	1	A AND NOT B
iv	1	1	0

We see that either row ii) OR row iii)  produces a 1, i.e

(NOT A AND B) OR (A AND NOT B)

From this expression, we draw the circuit as shown in the suggested response above.

Part c)

Data Lines (Input) are denoted as x₁…x₄, select line are denoted as s₁ and s₂, Output is denoted as f

Alternative Diagram in ASCII :

        _______________________
       |        4-to-1         |
D0 ----|      Multiplexer      |
       |                       |
D1 ----|                       |---> Output
       |                       |
D2 ----|                       |
       |                       |
D3 ----|_______________________|
              |         |
              |         |
              |         |
              |         |
              S1        S0
Data Lines (Input) are denoted as D0...D3, select line are denoted as S0 and S1.

See Note²

Part d) i)

16+8+0+2+1 =27

Explanation/Working:

(0×2⁷)+(0×2⁶)+(0×2⁵)+(1×2⁴)+(1×2³)+(0×2²)+(1×2¹)+(1×2⁰)

0+0+0+16+8+0+2+1=27

Part d) ii)

  0111 +
  1110
———-
10101 ← this result cannot be stored in 4 bits.

Part d) iii)

Largest number = 0111 =7 (Show conversion)
Smallest number= 1111= -ve 7 (Show conversion)

Part d) iv)

Suggestion solution 1:

Algorithm, copy all numbers from LSB to MSB up to and including the first 1, then flip remaining bits in that order, i.e
5= 0101

Applying algorithm : 1011

Suggestion solution 2:

+5= 0101
Ones = 0101+1 = 1010
Twos = 1010+1 = 1011

Links to Notes

Logic Gates – Formal Introduction

Multiplexers

Attributions to media used in this post

Inductiveload, Public domain, via Wikimedia Commons

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Footnotes

1. https://islandclass.org/2021/10/20/logic-gates-formal-introduction/ ↩︎
2. https://islandclass.org/2021/10/21/multiplexers/ ↩︎

© 2023  Vedesh Kungebeharry. All rights reserved. 

1. Part a) i)
2. Part a) ii)
3. Part a) iii)
4. Part b) i)
5. Part b) ii)
6. Part b) iii)
7. Part c)
8. Part d) i)
9. Part d) ii)
10. Part d) iii)

Part a) i)

        _______________________
       |        4-to-1         |
D0 ----|      Multiplexer      |
       |                       |
D1 ----|                       |---> Output
       |                       |
D2 ----|                       |
       |                       |
D3 ----|_______________________|
              |         |
              |         |
              |         |
              |         |
              S1        S0

Part a) ii)

Set the select inputlines to 01 to select the 2^nd line, and when input from the 4^th line is needed after 1 second (i.e i3), set the select input lines to 11

Part a) iii)

– It always exists in 1 of 2 stable states.
-It can retain its state to achieve storage (in the case the set goes from 1 to 0)

Can be used in RAM Arrays (to implement 1 bit storage) or to Implement a Ripple Counter

Part b) i)

1101

(First bit is 1 for to represent a negative value,

working for 5₁₀ to binary :

       2 | 5  

       2 |2  remainder 1

       2 |1  remainder 0 

            0  remainder 1

i.e 5₁₀  = 101₂

combining the result we get 1101₂

)

Part b) ii)

1010 (flipped bits of 0101)

Part b) iii)

1010 +1 = 1011

Part c)

(Show binary-decimal conversions)

For an unbiased exponent and unnormalized mantissa:

sign is -ve, Exponent = 2, Mantissa= 0101

i.e -0.0101 x 2_­² = -1.01

-1.01₂   =  (-1 x 2⁰)+ (0 x 2^-1)+ (1 x 2^-2)

          = -1 + 0+ ¼

          = -1.25

Part d) i)

Not (Unary operator)

x	Not X
0	1
1	0

Part d) ii)

AND

x	Y	X AND Y
0	0	0
0	1	0
1	0	0
1	1	1

Part d) iii)

OR

x	y	X OR Y
0	0	0
0	1	1
1	0	1
1	1	1

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© 2023  Vedesh Kungebeharry. All rights reserved.