1. Part a)
2. Part b)
   1. Explanation
3. Part c)
4. Part d) i)
   1. Explanation/Working:
5. Part d) ii)
6. Part d) iii)
7. Part d) iv)
8. Links to Notes
   1. Attributions to media used in this post
9. Footnotes

Part a)

AND Gate:

  A | B | A AND B
  ---------------
  0 | 0 |    0
  0 | 1 |    0
  1 | 0 |    0
  1 | 1 |    1

Or Gate:

  A | B | A OR B
  ---------------
  0 | 0 |    0
  0 | 1 |    1
  1 | 0 |    1
  1 | 1 |    1

Not Gate:

  A | NOT A
  ---------
  0 |   1
  1 |   0

See this note¹

Part b)

Suggested response:

XOR truth table:

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

Output is 1 in XOR for (NOT A AND B) OR (A AND NOT B)

Circuit:

Explanation

Assume we want to use an AND gate as a building block for our resulting circuit. Wherever we have an output of 1  it means that the inputs to that and gate should also be 1 .

If we imagine an AND gate being the last gate before the output, wherever there is a 1 we need to understand that the inputs to that gate would have to be 1.

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

-For each output that produces a 1, we modify the variable input to match  the modded input listed in the specific row of the table:

Row number	A	B	A XOR B	Desired output using AND Gate
i	0	0	0
ii	0	1	1	NOT A AND B
iii	1	0	1	A AND NOT B
iv	1	1	0

We see that either row ii) OR row iii)  produces a 1, i.e

(NOT A AND B) OR (A AND NOT B)

From this expression, we draw the circuit as shown in the suggested response above.

Part c)

Data Lines (Input) are denoted as x₁…x₄, select line are denoted as s₁ and s₂, Output is denoted as f

Alternative Diagram in ASCII :

        _______________________
       |        4-to-1         |
D0 ----|      Multiplexer      |
       |                       |
D1 ----|                       |---> Output
       |                       |
D2 ----|                       |
       |                       |
D3 ----|_______________________|
              |         |
              |         |
              |         |
              |         |
              S1        S0
Data Lines (Input) are denoted as D0...D3, select line are denoted as S0 and S1.

See Note²

Part d) i)

16+8+0+2+1 =27

Explanation/Working:

(0×2⁷)+(0×2⁶)+(0×2⁵)+(1×2⁴)+(1×2³)+(0×2²)+(1×2¹)+(1×2⁰)

0+0+0+16+8+0+2+1=27

Part d) ii)

  0111 +
  1110
———-
10101 ← this result cannot be stored in 4 bits.

Part d) iii)

Largest number = 0111 =7 (Show conversion)
Smallest number= 1111= -ve 7 (Show conversion)

Part d) iv)

Suggestion solution 1:

Algorithm, copy all numbers from LSB to MSB up to and including the first 1, then flip remaining bits in that order, i.e
5= 0101

Applying algorithm : 1011

Suggestion solution 2:

+5= 0101
Ones = 0101+1 = 1010
Twos = 1010+1 = 1011

Links to Notes

Logic Gates – Formal Introduction

Multiplexers

Attributions to media used in this post

Inductiveload, Public domain, via Wikimedia Commons

---

Footnotes

1. https://islandclass.org/2021/10/20/logic-gates-formal-introduction/ ↩︎
2. https://islandclass.org/2021/10/21/multiplexers/ ↩︎

© 2023  Vedesh Kungebeharry. All rights reserved.