The SR Flip-Flop – Practical Introduction

This post is used for discussion in class.

In class demonstration

Teacher draws a SR latch using NOR gates  with top gate as g1 and bottom gate as g2.


Teacher draws a truth table for quick reference:


  • Scenario, Circuit Startup S=0, R=0 , Q=0  (Q’ is irrelevant and can be proven in a later scenario)
    • Input G2 becomes 0,
    • Q’ becomes 1
    •  Input G1 becomes 1
    • Q stays at 0 , circuit is stable in a consistent state.

  • Scenario: circuit in previous state, S becomes 1, r stays at 0, Q was 0 and Q’ is 1

  • Scenario: Same as previous state,  however S returns to 0.
    (Memory is Achieved)

  • Same as previous State, but R is set to 1

  • Same as previous state but R returns to 0

  • CHAOS!!! S and R set to 1.

Media Attrbution

No machine-readable author provided. Arturo Urquizo assumed (based on copyright claims)., CC BY 3.0 <>, via Wikimedia Commons

© 2021  Vedesh Kungebeharry. All rights reserved. 

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