Thus far it is possible that we’ve made the assumption that a process usually runs to completion and then the OS runs other processes. As indicated in our process management note/discussion we now know this to be false.

It is possible for an OS to be implemented as a timing mechanism, switching between each process after say 100 instructions being executed. In theory, this is a good first approach if all instructions are executed in  a very short and equal timeframe.

Below, we  represent how this can be accomplished by observing what the cpu processes assuming each instruction takes about 1 second for 2 processes, P1 and P2:

Order of execution	Process/operation category	Instructions executed	Time taken (s)
1	I/O	I/O for OS and P1	2
2	P1	100 lines from P1	100
3	I/O	I/O for OS and P2	2
4	P2	100 lines from P2	100
. . . . .	. . . . .	. . . . .	. . . . .
501	I/O	I/O for OS and P1	2
502	P1	100 lines from P1	100
503	I/O	I/O for OS and P2	2
504	P2	100 lines from P2	100
. . . . .	. . . . .	. . . . .	. . . . .

In practice though, a single instruction from a running process can  be waiting or very long, such as when the instruction requires data be read from a secondary storage medium.  Data access on secondary storage is very slow.  Let us assume that P1 has  a few instructions that require some data access. Our table now becomes:

Order of execution	Process/operation category	Instructions executed	Time taken (s)
1	I/O	I/O for OS and P1	2
2	P1	100 lines from P1	1500
3	I/O	I/O for OS and P2	2
4	P2	100 lines from P2	100
. . . . .	. . . . .	. . . . .	. . . . .
501	I/O	I/O for OS and P1	2
502	P1	100 lines from P1	1200
503	I/O	I/O for OS and P2	2
504	P2	100 lines from P2	100
. . . . .	. . . . .	. . . . .	. . . . .

We observe in this analogy that p1 runs for a total of 1502 seconds P2 for 102, P1 for 1202 seconds, P2 for 102 seconds.

To the end user, It appears as if BOTH processes are running slowly, in the long run, p2 can appear to be running in slow motion!

To solve this problem, we could use a system of interrupts, i.e, interrupt the CPU whenever we anticipate a waiting period (for whatever reason I/O, system errors, device errors etc.)

In our analogy, every time P1 needs to wait on data from secondary access, we could put the rest of P1 in a waiting/blocked state and start processing P2.  When the hardware is finished gathering the data for P1, it could interrupt the execution of P2 and return control to P1.

Omitting IO from the OS, An illustration of this example is shown below:

(Assume that instructions for p1 are executed in 1 second intervals until an instruction needing secondary data access is reached)

P1’s instruction include:

49 short instructions then,

1 long access instruction then,

24 short instructions then,

1 long access instruction, then

25 short instructions

Order of execution	Process/operation category	Instructions executed	Time taken (s)
1	P1	50 lines from P1	50
2	OS	(P1 Blocked),	–
3	P2	100 lines from P2	100
4	P2	100 lines from P2	100
5	P2	100 lines from P2	100
6	P2	50 lines from P2, interruption occurs	50
7	P1	25 lines from P1	25
8	OS	(P1 Blocked),	–
9	P2	50 lines from P2	50
10	P2	100 lines from P2	100
11	P2	100 lines from P2	100
12	OS	Interruption occurs to return accessed data to P1	–
13	P1	25 lines from P1	25
14	P2	100 lines from P2	100
. . . . .	. . . . .	. . . . .	. . . . .

We now observe both processes running efficiently with no excessive wait times.

Exercise

1. What is the total wait time for P1 and P2 Respectively?
2. Which process had the more instructions executed?

© 2022  Vedesh Kungebeharry. All rights reserved. 

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